In conventional electrically programmable read-only memory (EPROM) cells, and more particularly electrically erasable and programmable read-only memory (EEPROM) cells, a "verify" operation is required to be performed after every programming operation in order to assure that the selected cell has been effectively programmed. A typical program/verify scheme is shown in the electrical circuit diagram of FIG. 1. A memory array indicated by the dashed enclosure 10 includes a plurality of memory cells 12,14 arranged in rows and columns. Each row of cells is connected by a corresponding word line WL.sub.0 -WL. Each cell is also a member of a bit line (one bit line 15 is shown) to which the drain 16 of every cell in the bit line is connected. The bit line is selected by a bit line tree decoder including transistors 18, 20 and 22; these are actuated, respectively, by signals YD2, YD1 and SEC.
In programming a cell, a programming voltage V.sub.PP, which for example may be 10 volts, is supplied through a row decoder or multiplexer 24 to a selected one of the word lines WL.sub.0 -WL. Meanwhile, a programming drain voltage V.sub.PROG is applied through a p-channel field effect transistor 26 and serially through the current paths of decoding transistors 18-22 to a drain 16 of the selected cell.
For each particular sector or other predetermined group of memory cells 12-14, a reference cell 28 is provided in order to determine whether or not a particular cell within the array 10 has been programmed. While a selected one of the cells 12-14 within the array 10 is being programmed, the reference cell 28 is also being programmed. For this purpose, a p-channel transistor 30 and pseudo tree decoder transistors 32, 34 and 36 are provided in order to apply V.sub.PROG to the drain of the reference cell 28, in emulation of the application of V.sub.PROG to the selected cell within the array 10. The programming voltage V.sub.PP is applied through a row decoder analog circuit 38 to the control gate 40 of the reference cell 28. After the application of a full programming pulse of magnitude V.sub.PP for a predetermined period of time, the programming voltages are disconnected from the circuit, as by making the PROG signal low, and a pair of verify voltage sources V.sub.VC and V.sub.VG are connected to the circuit, as by means of making a signal VERIFY go high. The "verify" voltage V.sub.VG to be applied to the control gate of the inspected cell is chosen as about 5 volts in the illustrated embodiment. A "verify" voltage V.sub.VD, for application to the drain of the selected cell, is applied when the VERIFY signal is high to the drain of the selected cell through decoding transistors 18-22. In the illustrated scheme, the source is grounded in both PROGRAM and VERIFY states.
To determine whether a selected cell has been appropriately programmed according to the prior art, the voltage at a node 42, which is coupled to the drain of the selected cell by the decoder transistors 18-22, is compared with the voltage present at a node 44, which in turn is coupled to the drain of the reference cell 28 through the current paths of decoder-emulating transistors 32-36. The voltages at nodes 42 and 44 are compared by a sense amplifier 46. As a selected cell becomes more and more programmed, its threshold voltage V.sub.t will grow and its drain to source current I.sub.DS will drop. The smaller the I.sub.DS current, the smaller the voltage drop that will be experienced at node 42. Hence, when the node 42 has a voltage which is less than the voltage drop at node 44, a programmed state will be declared by the sense amplifier 46 and the next cell will then be addressed.
According to this conventional practice, "verify" voltages are applied to the reference cell 28 each time a verification is performed on one of the cells in the memory array 10. Thus, the number of times that the reference cell 28 is accessed is several orders of magnitude greater than the number of times that any particular cell inside the memory array 10 is accessed. The reference cell 28 is generally programmed only once, while cells within the array 10 have a tendency to be programmed and refreshed, or programmed, erased and reprogrammed, several times. Therefore, as time passes, the danger increases that the reference cell 28 will begin to lose its programming, causing an increase in its I.sub.DS and a decrease in the voltage drop across the cell. When the voltage drop at mode 44 is compared in the verify state with the voltage at node 42 caused by the inspected cell in the array, the sense amplifier 46 may "pass" the cell as being programmed, while in actuality an insufficient amount of programming has occurred to the selected cell.
Another problem with a conventional program/verify sequence is that, typically a program pulse of a predetermined magnitude and period is applied to the memory cell each time programming is called for, regardless of the relative amount of programming to the floating gate of the cell needed. This creates the danger of overprogramming, because fractions of a programming pulse are unable to be applied to the cell. The overprogramming of selected cells in the array leads to a wider program V.sub.t distribution which in turn results in a wider erase V.sub.t distribution, limiting endurance; overprogramming also degrades the long term performance of the EEPROM cell.
Finally, the conventional method necessitates a separate VERIFY state having voltages different from the programming state. The VERIFY state takes time to enter into and exit from, thereby slowing down the programming process.
A need therefore exists for a programming method and apparatus that permits a variable programming pulse to be applied to the floating gate of the cell to be programmed and which avoids a separate VERIFY state.